Tracking Convergence
We can track external events to plan future integration test effort.
This project gets more relevant when RISCV-64 processors start appearing in appliances with more instruction set extensions and with code compiled by newer compiler toolchains.
The project results get easier to integrate if and when more development effort is applied to specific Ghidra components.
This page collects external sites to track for convergence.
Toolchains and platforms
binutils
New instruction extensions often appear here as the first public implementation. Check out the opcodes, aliases, and disassembly patterns found in the test suite.
- track the source
- inspect
git log include/opcode/|grep riscv|head - inspect
git log gas/testsuite/gas/riscv - track updates to the list of supported extensions
sample log
- 28 Feb 2024 - jiawei@iscas.ac.cn added support for Zabha riscv extension (atomic byte and half-word memory ops)
- 4 Jan 2024 - jinma@linux.alibaba.com fixed th.vsetvli for T-Head extensions
compilers
- track the source
- inspect
git log gcc/testsuite/gcc.target/riscv
log
Look for commits indicating the stability of vectorization or new compound loop types that now allow auto vectorization.
libraries
- track the glibc source
- track the openssl source
log
- glibc
- Not much specific to RISC-V
- openssl (in master, not released as of openssl 3.2)
- phoebe.chen@sifive.com added vector crypto implementations of AES-CBC mode, AES-128/192/256-CTR, AES-128/256-XTS
- jerry.shih@sifive.com added Zvksh support for sm3
kernels
- track the source
- inspect
git log arch/riscv
Note: the Linux kernel just added vector crypto support, derived from the openssl crypto routines. This appears to mostly be in support of encrypted file systems.
system images
- Fedora
- Ubuntu
cloud instances
- Scaleway risc-v servers
- with the T-HEAD TH1520 SoC, 16GB RAM and 128GB
RISCV International Wiki
The RISCV International wiki home page leads to:
ISA Extensions
- profiles and individual standards-tracked extensions
- vendor-specific extensions
- gcc intrinsics
Applications
- track source
- Look for use of riscv intrinsics with arm/Neon and avx2 equivalents as opposed to allowing compiler autovectorization.
- Watch for standardization of 16 bit floating point
Ghidra
similar vector instruction suites
Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc defines the instructions used by the AARCH64 Scalable Vector Extensions package.
This suite is similar to the RISCV vector suite in that it is vector register length agnostic. It was added in March of 2019 and not updated since.
pcode extensions
Ghidra/Features/Decompiler/src/decompile/cpp holds much of the existing Ghidra code for system and user defined pcodes.
userop.h and userop.cc look relevant, with caheckman a common contributor.
Community
- RISCV Organization
- reddit discussion group
- new RISCV products are often discussed here.